AGM CPLD AGRV2K
AGRV2K CPLDs is the low cost CPLDs. This instant-on, non-volatile CPLD family targets general-purpose and low-density logic. The logic density is 2K Logic Elements with LQFP-100(AGRV2K100) , LQFP-64(AGRV2K64) and LQFP-48(AGRV2K48) packages.
Low-Cost and low-power CPLD
Instant-on, non-volatile standard compatible architecture.
Up to 4 global clock lines in the global clock network that drive throughout the entire device.
Provides programmable fast propagation delay and clock-to-output times.
Provides PLL per device, clock multiplication, and phase shifting.
Supports 3.3-V logic level
Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
3.3-V LVCMOS and LVTTL standards
AGM CPLD AGRV2K
AGRV2K CPLDs is the low cost CPLDs. This instant-on, non-volatile CPLD family targets general-purpose and low-density logic. The logic density is 2K Logic Elements with LQFP-100(AGRV2K100) , LQFP-64(AGRV2K64) and LQFP-48(AGRV2K48) packages.
Low-Cost and low-power CPLD
Instant-on, non-volatile standard compatible architecture.
Up to 4 global clock lines in the global clock network that drive throughout the entire device.
Provides programmable fast propagation delay and clock-to-output times.
Provides PLL per device, clock multiplication, and phase shifting.
Supports 3.3-V logic level
Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
3.3-V LVCMOS and LVTTL standards
